1. Technical Field
Embodiments of the invention relate generally to interrupts for processors.
2. Background Art
An Advanced Programmable Interrupt Controller (APIC) is a programmable interrupt controller (PIC) that receives interrupt requests and provides interrupt outputs according to programmable procedures or priorities. Local APICs are used in processors (such as microprocessors). I/O APICs are used in chipset devices (such as an input/output (I/O) controller hub (ICH)) and peripheral devices. Examples of peripheral devices include device coupled to the ICH that are compatible with one of the Peripheral Component Interconnect (PCI) standards or one of the PCI Express (PCIe) standards such as the PCI Express® Base Specification Revision 2.0, Dec. 20, 2006, provided by the PCI-SIG®. An xAPIC is an extended APIC, which is similar to early APICs but with some additional features and in the xAPIC architecture, local and I/O APICs communicate through a system bus rather than through an APIC bus. A further Extended xAPIC includes additional extensions and features.
Processor packages may include more than one core, each of which may include more than one processor. Physical mode interrupts are interrupts for which an interrupting device designates a processor by a physical identification number or is broadcast to all processors. Logical mode interrupts are interrupts for which an interrupting device designates a processor or processors by a logical identification numbers or numbers. APIC interrupt deliveries include directed interrupts (single processor target), multi-cast (multiple processor target) and broadcast (all processors). In a lowest priority interrupt, a procedure is used to select a processor that is in the lowest processor priority to respond to the interrupt. Lowest priority may be decided in the chipset—often in an ad hoc fashion or with stale data of processor priority. Because the priority information is often not reliable, some chipsets merely select a particular processor (such as through a round robin technique) and provide the interrupt to that processor in a broadcast manner in which the other processors also receive the interrupts but do not respond to them.
The logical mode provides significantly greater flexibility in directed interrupts and is the mode used by Microsoft Windows & some Linux shrink-wrap operating systems. The logical mode of the xAPIC architecture provides an operating system software with flexibility in initializing the logical APIC identification number (ID), which is the unique identifier for each processor in the system. (The processors also have physical APIC IDs.) Other processors as well as devices or IOxAPICs use this ID to send interrupts to this processor. Given the flexibility in initialization of the logical xAPIC ID, there is no relationship between the actual physical topology of the platform and how the IDs are assigned. Although operating system initialization allows operating systems greater flexibility in grouping processors, at a platform level this complicates the routing of directed logical mode interrupts. Routing of logical mode interrupts is done through broadcasting the interrupts and having the local processor logic accept the interrupt if it matches its local APIC ID.
Having each processor check for every interrupt leads to both performance and power inefficiencies. For example, under a broadcast approach, each processor checks to see if the interrupt is directed to the processor although the processor is in a low power state. Since interrupts occur fairly often, it makes it difficult for a processor to stay in a deep low power state. Further, performance is reduced because there is traffic on interconnects in sending interrupts to packages for which the interrupt is not directed. Under one approach, an operating system has attempted to have a logical cluster of processors be for processors in the same package by assigning logical IDs in the order the processors are started. This approach provides only a partial solution if relied upon and broadcasting is still used. Accordingly, there remains a need for creating logical APICs that can be routed to processors in an efficient manner.